Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
EDN

Aldec’s Active-HDL 7.1 adds new simulation technology

SAN FRANCISCO — Aldec Inc. has released a new version of its Active-HDL 7.1 FPGA and ASIC design entry and verification platform, including several new tools. Aldec (Henderson, Nev.) said new tools ...
Design-Reuse

Aldec Enhances Award-Winning Active-HDL with Flexible File Management to Manage Complex FPGA Projects

Henderson, NV – September 24, 2012 – Aldec, Inc. today announced the immediate availability of Active-HDL™ 9.2, an HDL-based FPGA Design and Simulation solution now offering flexible file ...
EE Herald

Avnet to distribute Aldec's Active-HDL in Asia

Aldec, Inc., has announced that it has entered into a distribution agreement with Avnet Electronics Marketing Asia. Under the terms of the agreement, Avnet Electronics Marketing will promote and ...
New Electronics

Aldec platform supports newest fpga devices

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...