EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
EDN

Estimating Power Dissipation in CMOS Devices

This application note describes ways to estimate power dissipation of individual CMOS logic devices in a system. It will help users determine if their designs raise any power dissipation concerns. Due ...
Design-Reuse

Power Reduction Techniques for Ultra-Low-Power Solutions

The consumer demand for greater functionality and higher performance, but also for lower costs adds significant pressure on System-on-Chip (SoC) manufacturers. The continuing advances in process ...
Electronic Design

Understanding Low-Power IC Design Techniques

Low-power IC design techniques have been around for quite a while. They weren’t always required, though they were nice to have. The rapid growth of the consumer market for battery-powered devices has ...
Semiconductor Engineering

Emulation-Centric Power Analysis Of SoC Designs

Verification expert Lauro Rizzatti recently interviewed Jean-Marie Brunet, senior marketing director, Scalable Verification Solutions Division (SVSD), Siemens EDA, about the importance of accurate ...
Nature

Low-Power CMOS Flip-Flop Design and Power Management

Recent advances in Complementary Metal-Oxide-Semiconductor (CMOS) technology have underscored the importance of power-efficient flip-flop designs for modern electronic systems. Over recent years, ...